Instructor:H. Z. Fardi
Office Hours:TR 3:00-4:00PM
This course covers the fundamentals of Very Large Scale Integrated (VLSI) CMOS circuit design.It covers processing steps and device design of MOSFET used in Integrated Circuits (IC's).The physical relationship between circuit design and actual silicon layout and area is emphasized, as is the anticipated performance of the circuit as affected by typical variations in process parameters. This includes device modeling and circuit simulation using P-SPICE and Layout-Editor. This course gives students a full overview of digital integrated circuit design, covering from basic MOS physical operation to basic building block of digital circuits.
Text Book:Kang& Leblebici, CMOS Digital Integrated Circuits, 3rd edition.
This course is designed for EE senior undergraduate and first year graduate students with no previous IC processing and design experience. Familiarity with electronics (EE3225) and Pspice is highly recommended
References: (The following reference books are reserved in the Auraria Library for 2-hour checkout):
 Geiger, Allen, & Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, 1990.
John P. Uyemura, Physical Design of CMOS Integrated Circuits Using L-EDIT, 1995.
Projects ( 2-3 )30% ( oral presentation is required for one of these projects)
Midterm in-class exam: 20%
Final take-home Project: 30%.
Projects and homework’s must be turned-in on due dates.Late homework’s and projects will get partial credits.
Midterm Exam:Tuesday March 18th, 03
Final Exam:Tuesday May13th, 03
Material Covered From Textbook (Kang& Leblebici)
MOS Fabrication-Device LevelChap. 2
Fabrication Process Flow
Layout Design Rules
MOSFET Physical Operation: Device LevelChap. 3
Structure of MOS
Operation of MOS
Current-Voltage Characteristics of MOS
MOS Model Using PSPICE: Circuit LevelChap. 4
SPICE LEVEL –1
SPICE LEVEL –2
MOS Inverter: StaticChap. 5
Resistive Load Inverter
Active Load Inverter
MOS Inverter: SwitchingChap. 6
Propagation Delay Times
Switching Power Dissipation
Combinational MOS Logic-Transmission Gates Chap. 7 Sequential MOC Logic CircuitsChap. 8
Material Covered From Ref.:
LEDIT: Layout of nMOS, CMOS.Design of Integrated Circuits at chip level.
A project is assigned from this section.